1. Field of the Invention
The present invention relates to a speech codec and a method of processing a speech signal with a speech codec.
2. Description of the Prior Art
Speech codecs are usually implemented by digital signal processors (DSP). Since it has been difficult for a single DSP to both encode an analog speech signal and decode a digital speech signal, it has heretofore been customary to employ a plurality of codecs to implement a speech codec.
One conventional process of processing a speech signal with a speech codec will be described below. It is assumed in the conventional process that one frame is composed of four subframes and comprises 160 samples.
FIG. 1 of the accompanying drawings shows in block form a conventional speech codec composed of two DSP chips. FIG. 2 of the accompanying drawings shows a processing sequence of the speech codec shown in FIG. 1. A flow of signals in the speech codec will be described below with reference to FIGS. 1 and 2.
A DSP 1 has an encoder 101 for exclusively encoding a speech signal. The encoder 101 is supplied with PCM (pulse code modulated) data 102 at predetermined sampling intervals. The supplied PCM data 102 are stored in a PCM data input buffer 103. When an encoding process is started, one frame of PCM data is supplied from the PCM data input buffer 103 to a frame encoding processor 104, which encodes the supplied frame of PCM data.
Then, the PCM data from the frame encoding processor 104 are subjected to a subframe encoding process 1 by a subframe encoding processor 105 which outputs a series of encoded data to an encoded data series transmission buffer 109. Similarly, the PCM data from the frame encoding processor 104 are also subjected to subframe encoding subframe processes 2, 3, 4 by respective sub-frame encoding processors 106, 107, 108 which output respective series of encoded data to the encoded data series transmission buffer 109. Upon completion of all the subframe encoding processes, the encoded data series transmission buffer 109 transmits a series 110 of encoded data.
A DSP 2 has a decoder 111 for exclusively decoding encoded data. When a decoding process is started, the decoder 111 receives a series 112 of encoded data. The received series 112 of encoded data is supplied to an encoded data series reception buffer 113 which outputs the series 112 of encoded data to a frame decoding processor 114. The frame decoding processor 114 effects frame decoding processing of the supplied encoded data. Then, the encoded data from the frame decoding processor 114 are subjected to a subframe decoding process 1 by a subframe decoding processor 115 which outputs decoded PCM data 120 to a decoded PCM data output buffer 119. Likewise, the encoded data from the frame decoding processor 114 are also subjected to subframe decoding processes 2, 3, 4 by respective subframe decoding processors 116, 117, 118 which output decoded PCM data 120 to the decoded PCM data output buffer 119. The decoded PCM data output buffer 119 outputs the decoded PCM data 120 at certain sampling intervals.
FIG. 3 of the accompanying drawings illustrates a processing timing sequence of the conventional speech codec with two DSP chips. It is assumed that a storage buffer capable of storing one subframe of PCM data is referred to as a storage area. According to the conventional process using the speech codec, the buffers for inputting and outputting PCM data are required to have four storage areas for DSP 1 and four storage areas for DSP 2, and hence at least a total of eight storage areas. Ideally, encoding and decoding processes should be carried out with such timing that the encoding process is started at the same time that the storage of one frame of PCM data in an input buffer is completed, and in the decoding process decoded PCM data produced by the first subframe decoding process are outputted to an output buffer at the same time that the outputting of one frame of decoded PCM data is completed.
Actually, in view of timing shifts or errors of the encoding and decoding processes, the input buffer used in the encoding process is required to have (4+.alpha.) storage areas and the output buffer used in the decoding process is also required to have (4+.alpha.) storage areas.
For mobile communication networks, there is a provision stipulating that a series of encoded data transmitted from an encoder should be received by a decoder within a time period of several milliseconds, e.g., 5.75 milliseconds for a unified European digital automobile telephone from the start of transmission from the encoder. This provision can be satisfied by the conventional speed codec with two DSP chips because the two DSP chips can operate fully independently of each other.
Improved DSP performance allows a single DSP chip to both encode and decode speech signals in a speech codec. If the above provision regarding the time period between the start of transmission from the encoder and the start of reception by the decoder is to be met, the conventional processing method in which the encoding and decoding processes are executed independently of each other is required to start the encoding process before the decoding process is finished.
If the encoding process is to be carried out by an interrupt routine, control cannot return to the decoding process unless the encoding process in the interrupt routine is ended. Therefore, the outputting of decoded PCM data produced by the decoding process is delayed, preventing synthesized voice sounds from being outputted normally.